Design of a Novel 32x32 SRAM Array with and without Pipelined Technique for High Speed, Low Area and Low Power Memory Applications

Abstract

Currently, each and every portable electronic device requires compact processor with high memory capacity. It is possible in VLSI (Very large scale integration) by using compact memory structure in order to achieve low power and low area applications. Large size SRAM needs high delay and low speed. To overcome this problem, the pipelined technique is incorporated into the SRAM Array structures to gain high speed and minimal delay.  Initially, the 6T SRAM and 9T SRAM cell are constructed by using latest CMOS technique. The functionality of these both SRAM is verified through the simulation process. From the obtain results, it shows that the 6T SRAM needs low die size and low power consumption compared to 9T SRAM cell. The main aim of this research work is to design 32x32 SRAM array by using 6T SRAM cell with 22nm advanced nano technology. The 32x32 SRAM array architecture consists of 5-32 bit row and column decoder, write driver circuit, Precharge circuit, 32x32 6T SRAM cell and  sense amplifier circuit. It requires less number of transistors and low power when compared to pipelined 32x32 SRAM ARRAY. But the delay is very high. Pipelined techniques is nothing but inserting D flip-flops into the appropriate location of 32x32 SRAM array to perform fetch, decode and execute operation very fast for each clock cycles. Hence pipelined based 32x32 SRAM array offers high speed and low transient delay than the 32x32 SRAM array without pipelined scheme.