Digital Circuits Layout Design using Transistor Sizing

Abstract

This paper introduces a novel heuristic transistor sizing technique aimed at optimizing Very LargeScale Integration (VLSI) circuit designs within the framework of a standard cell design approach. Inherent in this approach is the challenge of managing transistor dimensions to mitigate unnecessary upsizing and downsizing, which can lead to unwarranted increases in transistor widths. The proposed technique not only effectively addresses this challenge but also yields significant improvements in circuit delay and power efficiency. To validate the proposed method, the study focuses on the layout design aspect, utilizing the cadence virtuoso-90nm platform and leveraging the Ncell and Pcell methodology. This strategic approach results in an impressive 34% reduction in overall layout area, showcasing the practical utility of the heuristic transistor sizing technique. Additionally, by implementing the transistor sizing strategy judiciously, the paper attains notable reductions of 4-15% in both circuit delay and power consumption. The findings of this research underscore the substantial impact of the proposed approach on VLSI circuit optimization. By offering a solution to the transistor sizing challenge and its subsequent effects on circuit performance, this work provides a valuable contribution to the field, presenting a comprehensive method for enhancing the efficiency and effectiveness of VLSI circuit design.