March_Select_17n: Novel BIST Algorithm and Architecture

Abstract

Due to technology trends, variations in VLSI chip designs led to the test methods evolving from the existing ones to become highly efficient, commendable, and adaptable to the new test designs. Especially in embedded SoCs, built-in self-test (BIST) has traditionally become a necessary part in addition to the core logic that provides at-speed testing using a course of algorithms assigned for intended fault coverage. However, in recent test methods like March AB, which cover all static and dynamic faults with the help of larger test sequences due to increased core memory size, this led to increased testing time rather than functioning time. Aiming to reduce test time and test length complexity, a new March algorithm, March_Select_17n is proposed in this paper that works on the selection of essential March elements from the given set of algorithms, resulting in redundancy reduction. Initially, the March Select-46n algorithm is proposed to address the fault coverage issues. Further, by considering a few high fault coverage March algorithms through which each term from an individual algorithm will be eliminated on the basis of repetitive term after comparing it with the term that comes from previously applied algorithms in the pipeline.  Hence forth, achieved the final optimized March_Select_17n sequence. For the implementation of this new March_Select_17n algorithm, a novel BIST architecture setup is proposed incorporating new modules like compare and filter. In addition, it aims to cover undefined faults too, which are not seen in any of the existing literature as of now. The simulation results observed with test speed improvement of 86% compared with other existing algorithms that overcome the test latency problem.