Verification and Testing of Flash Controller through Hierarchical DFT

Abstract

Many SOCs today are too large for a traditional flat or partition-based approach to DFT with manual steps. Breaking designs into smaller pieces makes physical implementation more manageable for designers as well as for EDA tools. Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. For the purpose of ATPG, a well-proven D-algorithm is made use of. Vectors are created within the chip's DFT framework using Cadence's Modus tool at the 16nm technology node. These vectors cover various test modes, encompassing both stuck-at and transition faults. Each DFT region aims for over 99% stuck-at fault coverage and more than 85% transition fault coverage. If the target coverage (>=99% stuck-at fault coverage and >=85% transition fault coverage) is not met, fault coverage accounting method is utilized which considers untested faults from ATPG and generates test vectors making them testable resulting in coverage improvement. Before application on actual silicon in the ATE, these patterns undergo validation via simulation using Cadence's IES tool, at both block and device levels.