Design and Analysis of Phase Locked Loop for SPI and I2C protocols

Abstract

Phase locked loops (PLL) is mainly used in Communication-Systems, Micro-Processor, Networking , as well as Frequency-Synthesizers which are used in Clock-Generation along with Clock-Recovery. PLL(Phase-locked loops) being extensively utilized in digital systems which require higher performance for generating On chip clocks which have been well timed. Our Current Wireless systems of communications utilize PLL(Phase-Locked Loop) primarily to reduce Synchronization , the Clock-Synthesis, as well as skewing and jitter. Due to circuit operations increased speed, a faster locking capability circuit of PLL is needed. Here different blocks of PLL such as Phase detector, Charge Pump, Low Pass Filter and VCO are designed and focused to attain frequency of 3.5MHz for high speed mode of I2C protocol and default operating frequency of 1MHz for SPI protocol. Developing a Layout for the final design. The PLL blocks are implemented in CADENCE Virtuoso(90-nm) technology.