Comparative Analysis of 16-bit and 32-bit RISC Pipelined Processors by Verilog Design

Abstract

The evolution and advancement of microprocessors has driven the quest for enhanced performance and efficiency, particularly within the domain of Very-Large- Scale Integration (VLSI) design. The Reduced Instruction Set Computer (RISC) architecture is designed to execute small, uniform instructions efficiently, aiming to minimize the complexity, cost, cycle time, and energy usage of microprocessors. Although 16-bit RISC processors emerged in the 1970s, they encountered significant technical challenges, leading to the evolution of more advanced RISC processors with the use of pipelining architectures. This paper presents a comparative study of 16-bit and 32-bit RISC processors, each integrated with Floating Point Units (FPUs) and distinct instruction sets. The RISC processor with 16 bits utilizes a non- pipelined Harvard architecture employing independent data and instruction storage memories, while the 32-bit RISC microprocessor features a pipelined design inspired by the MIPS architecture. Both processors include General Purpose Registers (GPRs) and Flag registers (e.g., Carry, Zero). The study involves simulating and optimized floating-point units (FPU) and focusing on optimizing the data path, as arithmetic and logical operations significantly impact power consumption and execution delay. Therefore, comparing the two models, their performance and instruction sets were assessed, including speedup and power dissipation. Each model was designed in Verilog, simulated, and then integrated into a top-level component with the ISE Design Suite XILINX 14.4, with a detailed power analysis provided and also synthesized in Cadence genus and obtained timing analysis.