Design of Efficient Wallace Tree Multiplier using adders and Compressors

Abstract

Wallace Tree multiplier is frequently used in VLSI for effective binary multiplication, which is necessary in domains such as digital signal processing, embedded systems, and machine learning. Half and full adders increase area and delay in traditional designs. To improve performance, compressor-based systems like 3:2 and 4:2 compressors are incorporated, reducing power consumption, improving scalability, and simplifying partial product summing. This method is suitable for FPGAs, DSPs, and other high-performance applications because it strikes a better balance between speed and area. Overall, compressor-based optimization enhances performance and reduces latency, which has pushed developments in next-generation digital multiplier architecture.