Implementation of 1024 Point FFT with SIMD and Pipelined Execution for GPR Applications

Abstract

A high-throughput, hardware-efficient 1024-point parameterized Fast Fourier Transform (FFT) processor is developed for real-time Ground Penetrating Radar (GPR) subsurface imaging applications. The architecture employs a pipelined Radix-4 Single Instruction Multiple Data (SIMD) processing scheme and is implemented on the SCL 180 nm CMOS technology node using Cadence Genus and Innovus design environments. To reduce memory requirements, a quarter-wave symmetry compression technique is utilized for twiddle-factor storage, achieving a 75% reduction in Look-Up Table (LUT) memory footprint. The physical design is optimized through logic synthesis and layout constraints, maintaining a core utilization ratio between 60% and 70%. Static Timing Analysis (STA) verifies successful timing closure with a positive setup slack of +1.649 ns at an operating frequency of 60 MHz. Power characterization reports a total core power consumption of 103.68 mW, with 92.31% attributed to sequential internal switching activity, demonstrating the effectiveness of the reduced-stage pipelined architecture. The implementation achieves a balanced trade-off among throughput, memory efficiency, timing performance, and power consumption, making it suitable for ASIC-based GPR signal-processing systems.