Design of State Transition Graph Based Low Power Sequential Multiplier: RTL-to-GDS II Flow

Abstract

The reduction of energy has been a significant problem in the design of modern VLSI circuits, in particular for the multiplier circuits that are extensively used in DSP, communication and embedded computing applications. This work proposes a low power Predictive Activity-Gated State Transition Graph (PAG-STG) sequential multiplier that reduces unnecessary switching activity for low dynamic power dissipation. The proposed architecture incorporates an Activity Prediction Unit (APU) and fine grain datapath gating logic to activate the arithmetic blocks only when the computation is required. The multiplier was designed in Verilog HDL and realized through a full RTL-to-GDSII design flow using Cadence Genus and Innovus tools in 45 nm technology. The design was verified through full ASIC implementation flow which includes functional simulation, synthesis, timing verification, physical design and sign-off analysis. Experimental results show that, the PAG-STG multiplier achieves significant power efficiency and silicon utilization improvement without loss of computational accuracy. By minimizing redundant signal transitions, the proposed PAG-STG multiplier achieves improved energy utilization and becomes a practical solution for power-conscious ASIC and VLSI designs.