Enhanced Quantum FTRA with Integrated Fault Masking, Detection and Localization Mechanism

Abstract

Quantum circuits are susceptible to errors and building a fault tolerant reliable quantum circuit is critical.  This paper proposes a hybrid Quantum Fault Tolerant Reversible Adder/Subtractor with fault masking, detecting and locating mechanism. The presented hybrid reversible gate design with parity preserving reversible gates that enabled better circuit robustness was implemented using IBM Quantum Composer. To overcome the faults and enhance overall circuit robustness a Triple Modular Redundancy (TMR) based approach is integrated with the 3-bit majority voter circuit. Additionally, fault detection and locating mechanisms are also used to detect the fault occurrence. Simulation studies for the presented quantum circuit design was also verified using IBM Quantum Simulator. The results obtained confirmed that the combination of fault masking, detection and locating mechanisms improved the overall performance and reliability of the quantum circuit. The overall framework proposed provides a practical model for the development of a fault tolerant reversible logical circuits for various quantum applications