Design and Development of Concurrent Vedic Architecture using ASIC Design Flow

Abstract

The proposed research paper discloses the design and development of the Concurrent Vedic Multiplier Architecture using ASIC design flow. In this development process, the traditional Vedic principles are referred for the design of the multiplier architecture. The principles are converted into the Boolean statements and described using HDL language. The development process is further carried out through simulation, synthesis, RTL extraction, tight optimization and analysis. Different variants of the Xilinx FPGAs are preferred for concurrent implementation and ASIC design flow is then deployed for tight optimization using Cadence tool.