Implementation of 16 Bit SFRG Test Patterns for Detecting Faults on LBIST

Abstract

Defects have increased as a result of manufacturing issues brought on by the ever-increasing transistor count on chips and the shrinking feature size. For any Very Large Scale Integrated (VLSI) design, testing has thus become essential. Due to the length of the design cycle, the test procedures used to test those designs are disregarded as the design engineers focus more on design development. Any design must be 100% fault-free in order to pass, and the Design for Testability (DFT) technique makes it easier to find the errors. Different standards have been developed to test various integrated circuit components. In this paper fault coverage of Logic Built In Self-Test (LBIST) is designed and implemented for 16 bit test pattern using SFRG to get maximum fault coverage with detection of faults compare to other Pattern generators and it also gives the area, power and better efficient  using this test pattern. The design is coded in Verilog, verified for functionality using Xilinx ISIM simulator.