A Novel Low Leakage Power Reduction CMOS Design Technique

Abstract

The paper is based on the idea of new approaches for low- power CMOS circuit design using several techniques in minimizing power consumption and delay. Among these, the Multiple Threshold Voltage (MTCMOS) technique employs the use of transistors with different threshold voltages to allow the circuit to save power by selecting higher threshold voltages whenever full performance is not required. Another technique is Variable Threshold Voltage (VTCMOS), in which threshold voltage is adjusted dynamically according to circuit's operational state. This helps reducing leakage power during inactive states, while ensuring high performance during operational states. In the width modulation method, the width of the transistors is adjusted, which helps optimize both power consumption and performance by balancing the drive strength and leakage current.

The design is simulated using LTspice simulation software based on 90nm, 65nm, and 45nm CMOS Bulk Predictive Technology Models (PTM), which reflect the real-world semiconductor technologies. The results are that the new design approach greatly reduces power consumption, lowers delay, and maintains signal integrity, such that the output signal is still accurate and reliable despite the power-saving techniques. Overall, this novel design method can effectively reduces the power consumption, delay and retain the quality of the output signal in CMOS circuits.