Design and Hardware Realization of a Synthesis-Aware Layered LDPC Decoder with Deterministic Multi-Bit Fault Validation for SDR Applications

Abstract

As Software Defined Radio (SDR) platforms advance to meet 5G New Radio(NR) standards, the need grows for hardware-efficient error correction methods that maintain high throughput while allowing architectural adaptability. This paper introduces a fully synthesizable, RTL-based LDPC codec framework tailored for incorporation into high-speed SDR pipelines. In contrast to traditional behavioral implementations, the proposed system uses a synthesis-aware approach to guarantee compatibility with FPGA-based SDR front-ends, incorporating a zero-latency combinational encoder and a pipelined layered decoder. One major contribution of this work is the implementation of a deterministic fault injection mechanism at the hardware level, allowing for accurate testing of multi-bit error recovery a key necessity for ensuring link reliability in changing SDR settings. Using a 127/128-bit code word for 64-bit data, functional verification shows the system can correct three dispersed bit errors in about 10 clock cycles. Timing analysis shows stable convergence around 100 ns with a 100 MHz clock, and synthesis on a Xilinx Spartan-6 FPGA verifies a small logic foot print just 130 Slice LUTs and an estimated maximum operating frequency of 360.376 MHz. These results confirm that the proposed architecture is a strong, low-latency solution suitable for high-throughput 5 G NR SDR systems that demand dependable multi-bit error resilience.